1. Field of the Invention
Embodiments of the invention relate to solid state memory devices, and more particularly, in one or more embodiments, to repair of defective memory elements.
2. Description of the Related Art
Solid state memory devices have been widely used as data storage in various electronic devices. Types of solid state memory devices include volatile memories (for example, dynamic or static random access memories) and non-volatile memories (for example, read-only memories and flash memories).
FIG. 1 is a block diagram of a conventional solid state memory device 100. The illustrated memory device 100 is a dynamic random access memory (DRAM). The memory device 100 includes a memory array 102 to store data. The illustrated memory array 102 includes four memory banks 104a-104d (Bank 1 to Bank 4). A skilled artisan will, however, appreciate that the number of memory banks is not limited to a particular number, and that the number can vary widely, depending on the design of the memory device. Each of the memory banks 104a-104d includes an array of regular memory cells arranged in rows and columns. The memory device 100 may also include redundant memory arrays that include redundant memory cells. The redundant memory cells may be used to replace defective regular memory cells.
The memory device 100 also includes an address register 112, a row address multiplexer 114, a bank control logic circuit 116, and row address latch and decoder circuits 118a-118d. Each of the row address latch and decoder circuits 118a-118d is typically associated with a respective memory bank 104a-104d. The memory device 100 also includes a column address counter/latch 120, column decoders 122a-122d, a command execution logic circuit 130, and an address input 133. Each of the column decoders 122a-122d is typically associated with a respective memory bank 104a-104d. The memory device 100 further includes sense amplifiers 106a-106d, a column circuit 124, a data input register (or buffer) 126, and a data output register (or buffer) 128. Each of the sense amplifiers 106a-106d is typically associated with a respective memory bank 104a-104d. The memory device 100 also includes a status register 150.
The address input 133 receives address signals A0-A11 and bank address signals BA0, BA1 from an associated electronic device (for example, a CPU in a computer) through an address bus 134. The address register 112 may initially receive a row address and provide it to the row address multiplexer 114. The row address multiplexer 114 typically passes the row address to a selected one of the row address latch and decoder circuits 118a-118d, according to the state of the bank address signals. The selected one row address latch and decoder circuit stores the row address and applies various signals to the associated memory bank, thereby accessing a selected row address.
The address register 112 also receives a column address through the address input 133, and provides it to the column address counter/latch 120. The column address counter/latch 120 provides the column address to one of the column decoders 122a-122d, depending on the state of the bank address signals. The one column decoder provides the column address to the column circuit 124. The column circuit 124 provides signals to the selected memory bank to access a selected set of memory cells in the memory bank 104a-104d. Data can be written in the selected set of memory cells through the data input register 126 via a data port 143. The data port 143 can include a plurality of pins DQ0-DQ15 to provide data in a parallel form. Alternatively, data can be read from a selected set of memory cells through the data output register 128 and the data port 143.
The command execution logic circuit 130 serves to control the operations of the memory device 100 upon receiving various signal, including a clock enable signal CKE, a clock signal CLK, a chip select signal CS#, a write enable signal WE#, a column address strobe signal CAS#, and a row address strobe signal RAS#. The command execution logic circuit 130 can include a state machine 131 and a mode register 132. The state machine 131 and the mode register 132 together serve to control states of operations performed on the memory array 102.
Referring to FIG. 2A, an example memory bank in the memory array of a conventional memory device will be described. Each of the banks 104a-104d of FIG. 1 can have the same configuration as the bank 200 shown in FIG. 2A. The illustrated memory bank 200 includes first and second half banks 201a, 201b. Each of the half banks 201a, 201b includes a first block 202a and a second block 202b. Each of the first and second blocks 202a, 202b includes sub-arrays 210 of memory cells. Each of the half banks 201a, 201b can also include global redundant sub-arrays 250 between the first and second blocks 202a, 202b. 
Referring to FIG. 2B, a portion of the memory bank 200 of FIG. 2A will be described. For example, the portion of the memory bank can include four sub-arrays 210 that are arranged vertically, as indicated by 2B in FIG. 2A. The illustrated portion of the memory bank 200 includes first to fourth sub-arrays 210a-210d, first and second global input/output (I/O) lines 230a, 230b, and first to fourth local input/output (I/O) lines 240a-240d. 
Each of the sub-arrays 210a-210d may include first to fourth cores 220a-220d. Each of the cores 220a-220d may include memory cells arranged in a matrix form. The details of the cores 220a-220d will be described in connection with FIG. 2C.
The global I/O lines 230a, 230b serve to transmit data between the local I/O lines 240a-240d and the data port of the memory device (for example, the data port 143 in FIG. 1). The global I/O lines 230a, 230b extend in a column direction in the illustrated example. The first global I/O line 230a extends in a gap between the first and second cores 220a, 220b of the sub-arrays 210a-210d. The second global I/O line 230b expends in a gap between the third and fourth cores 220c, 220d of the sub-arrays 210a-210d. The global I/O lines 230a, 230b may be positioned at a different elevation from the cores 220a-220d. For example, each of the global I/O lines 230a, 230b may include four lines for transmission of four data digits.
The local I/O lines 240a-240d serve to transmit data between the cores 220a-220d and the global I/O lines 230a, 230b. The local I/O lines 240a-240d extend in a row direction in the illustrated example. The first local I/O line 240a extends in a space between the first and second sub-arrays 210a, 210b. The second local I/O line 240b extends in a space between the second and third sub-arrays 210b, 210c. The third local I/O line 240c extends in a space between the third and fourth sub-arrays 210c, 210d. The fourth local I/O line 240d extends in a space between the fourth sub-array 210d and another sub-array (not shown) below the fourth sub-arrays 210d. The local I/O lines 240a-240d may be positioned at an elevation the same as or different from the cores 220a-220d and the global I/O lines 230a, 230b. For example, each of the local I/O lines 240a-240d includes four lines for transmission of four data digits.
Referring to FIG. 2C, one of the sub-arrays and adjacent local and global I/O lines of the portion depicted in FIG. 2B will be described in more detail along with a global redundant sub-array. The illustrated portion includes a sub-array 210, first to eighth sense amplifiers 225a-225h, first and second global I/O lines 230a, 230b, first and second local I/O lines 240a, 240b, and first to fourth read/write gap circuits 275a-275d. The sub-array 210 may include first to fourth cores 220a-220d. The first to fourth sense amplifiers 225a-225d can be referred to as top sense amplifiers, and the fifth to eighth sense amplifiers 225e-225h can be referred to as bottom sense amplifiers in the context of this document. The illustrated portion also includes a global redundant sub-array 250 and a local redundant array 260 for the repair of defective memory cells or columns.
Each of the cores 220a-220d includes an array of memory cells (not shown), data lines (such as digit lines B1-Bn, T1-Tn), and access lines (such as word lines; not shown). The data lines extend in a column direction, and are coupled to memory cells arranged in the column direction. The access lines extend in a row direction that is perpendicular to the column direction, and are coupled to memory cells arranged in the row direction. In the illustrated example, the data lines includes top data lines T1-Tn, and bottom data lines B1-Bn. The top data lines T1-Tn of one of the cores 220a-220d are coupled to the top sense amplifier 225a-225d adjacent to the core while the bottom data lines B1-Bn of the core are coupled to the bottom sense amplifier 225e-225h adjacent to the core. The cores 220a-220d are arranged in a row direction. In the illustrated example, each of the cores 220a-220d may include 256 data lines: 128 top data lines and 128 bottom data lines. In the illustrated example, a single “column” may refer to a group of eight (8) adjacent data lines.
The sense amplifiers 225a-225h are coupled to either the first or second local I/O line 240a, 240b. In the illustrated example, the top sense amplifiers 225a-225d are coupled to the first local I/O line 240a whereas the bottom sense amplifiers 225e-225h are coupled to the second local I/O line 240b. The sense amplifiers 225a-225h are configured to detect the data levels of selected memory cells in the cores 220a-220d and transmit them to the local I/O lines 240a, 240b during read operation.
The first and second global I/O lines 230a, 230b extend in the column direction. The details of the first and second global I/O lines 230a, 230b can be as described earlier in connection with FIG. 2B.
The first local I/O line 240a includes first to fourth lines LIO1-LIO4 that extend in the row direction across a first region 223a that is outside the cores 220a-220d and adjacent to the first to fourth sense amplifiers 225a-225d. The second local I/O line 240b includes fifth to eighth lines LIO5-LIO8 that extend in the row direction across a second region 223b that is outside the cores 220a-220d and adjacent to the fifth to eighth sense amplifiers 225e-225h. The details of the first and second local I/O lines 240a, 240b can be as described above in connection with FIG. 2B.
The first to fourth read/write gap circuits 275a-275d provide electrical connection between the local I/O lines 240a, 240b and the global I/O lines 230a, 230b. In the illustrated example, the first read/write gap circuit 275a electrically couples the third and fourth lines LIO3, LIO4 of the first local I/O line 240a to the first global I/O line 230a. The second read/write gap circuit 275b electrically couples the first and second lines LIO0, LIO2 of the first local I/O line 240a to the second global I/O line 230b. The third read/write gap circuit 275c electrically couples the fifth and sixth lines LIO5, LIO6 of the second local I/O line 240b to the first global I/O line 230a. The fourth read/write gap circuit 275d electrically couples the seventh and eighth lines LIO7, LIO8 of the second local I/O line 240b to the second global I/O line 230b. 
The global redundant sub-array 250 includes columns of memory cells that can replace defective columns of memory cells in the cores 220a-220d. In the context of this document, the term “defective column” refers to a column that has one or more defective memory cells. In the illustrated example, the global redundant sub-array 250 includes 32 columns, that is, 256 data lines (for example, 128 top data lines and 128 bottom data lines). The global redundant sub-array 250 may have the same configuration as one of the cores 220a-220d. The global redundant sub-array 250 can be provided with its own sense amplifiers 227a, 227b. Data digits may be read from or written onto the memory cells in the global redundant sub-array 250 directly via a separate set of global I/O lines and local I/O lines. In the illustrated example, each bank (for example, 200 of FIG. 2A) includes four global redundant sub-arrays (32×4=128 columns) of the same configuration. The four global redundant sub-arrays form a global redundant array that can collectively repair one of the sub-arrays 210 (four 32-column cores=128 columns) in its entirety when there is a defective local I/O line that prevents access to the sub-array. For each group of four sub-arrays 210, there can be one global redundant sub-array 250, as shown in FIG. 2A although only one sub-array 210 and one global redundant sub-array are depicted in FIG. 2C.
The local redundant array 260 may include a column(s) of memory cells that can replace a defective column(s) of memory cells in the cores 220a-220d. The local redundant array 260 may have a less number of columns than one of the cores 220a-220d. The local redundant array 260 can be provided with its own sense amplifiers 228a, 228b. Data digits may be read from or written onto the local redundant array 260 directly via a separate set of global I/O lines and local I/O lines. The local redundant array 260 may be used when two or more of the sub-arrays 210 (for example, in FIG. 2A) include defective columns at the corresponding column addresses.
During a read or a write operation, a column address and a row address are provided to the memory device, as described above in connection with FIG. 1. The column address selects a column in one of the cores 220a-220d. The column can include, for example, eight adjacent data lines in the core. For example, a column address can select four top data lines and four bottom data lines alternating with one another in one of the cores 220a-220d. The row address selects a single word line coupled to a row of memory cells.
During read operation, the memory cells coupled to the selected data lines and word line are electrically coupled to a respective one of the sense amplifiers 225a-225d. The sense amplifier 225a-225d detects the data levels stored in the memory cells. The detected data levels are transmitted as data digits to the global I/O lines 230a, 230b via the local I/O lines 240a, 240b and the first to fourth read/write gap circuits 275a-275d. For example, the data levels on selected eight memory cells in the first core 220a can be read by the first and fifth sense amplifiers 225a, 225e, and transmitted to the global I/O lines 230a, 230b via the first and second local I/O lines 240a, 240b and the first to fourth read/write gap circuits 275a-275d. 
Similarly, during write operation, data is transferred from the global I/O lines 230a, 230b to the local I/O lines 240a, 240b via the read/write gap circuits 275a-275d. The data is then written to the memory cells coupled to the selected data lines and word line.
During production of a memory device, a test is typically performed to determine if there is any defect in the memory device. In certain instances, one or more local I/O lines in the memory device may have a defect. In such instances, a sub-array that uses the defective local I/O line for data transmission cannot be accessed. In the example shown in FIG. 2C, such a sub-array (that includes four cores 220a-220d having a total of 128 columns) can be replaced in its entirety with the four global redundant sub-arrays 250 (having a total of 128 columns) in the bank 200 (FIG. 2A).